Tutorial: handling PLL frequency multipliers circuits in 18F2550 to generate maximum speed of 48 Mhz.
Operation of 18F2550 with an external crystal of 20 Mhz:
Bolt 18F2550 system uses an external crystal 20 Mhz. However, due to its frequency multiplier circuit PLL (Phase Locked Loop), the effective rate is 48 Mhz and the speed of your USB port is 12 Mbps.
The figure below shows the block diagram of the clock generation system for both the CPU and to the USB port circuits.
In the particular case 18F2550 Bolt system, its configuration registers are already initialized via their bootloader firmware, so that the user will operate directly on the effective speed indicated above.
The 18F2550 receives the signal from the external crystal and use a prescaler that divides its frequency (depending on its configuration registers), from one of the following values: 1, 2, 3, 4, 5, 6, 10, or 12. The PLL circuit input must be consistently 4 Mhz. For operation at 20 MHz, the prescaler is dividing by 5.
These 4 MHz pass through the PLL and generates at its output 96 Mhz, which in turn are divided by 2 to give finally 48 MHz signal. This allows a speed of 12 Mhz in the USB port to communicate with any host computer.
Configuration registers for 48 Mhz operation:
300000H CONFIG1L= 24H
USBDIV=1: Clock of USB comes from 96 Mhz output divided by 2.
CPUDIV1=0,CPUDIV0=0: Principal oscilator (20 Mhz) is used as system clock.
PLLDIV2=1,PLLDIV1=0,PLLDIV0=0: Divides by 5 the frequency of external oscillator (20 Mhz)
IESO=0: function of automatic switching of oscillator is disabled.
FCMEN=0: fuction of automatic monitoring of oscillator is disabled.
FOSC3=1,FOSC2=1,FOSC1=1,FOSC0=0: external high frequency (20 Mhz) oscillator and PLL activated.